Brief
DIYAudio thread
http://www.diyaudio.com/forums/showthread.php?s=&threadid=111090
There are some kind of "DAC".
- Voltage magnitude: very common, R-2R DAC.
- Current Magnitude and accumulation: common for comercial
DAC IC, or my PowerDAC.
- PCM-PWM conversion: TI PurePath, etc. TAS-4i.
There are one more way,
Sound Pressure "Air" magnitude and acumulation.
There are some investigation for full digital speaker, using multi-unit
or multi-voice coil.
I want to DIY one for me, and listen the true digital sound.
PCM signal can be converted like below.
15 Elements: driven by D14 to D11, "numbers" driven by upper 4 bits.
(15 driven to 0 driven)
11 elements: driven by D10 to D0, "voltage magnitude" driven. Reference
Voltage to 1/2048 voltage.
(D15 represents + / - drive voltage)
There are 26 speaker elements per channel, so I need 26 small amplifier
per channel.
Schematic
- PCM Data is converted to 15 bits Number-accumulation and 11
bits voltage-driven.
- Voltage Reference works as Volume Control
- Analog switch for Voltage Reference, driven by each data bit
- Pre LPF after analog switch for each bit
Schematic
PCB
Very huge...
Ver.02
Ver01 is too huge and expensive. This is because amplification section.
Ver.02 will be changed to,
- 5V single drive
- There are no differential drive at each bit, drive voltage
is calculated at one point for each channel.
- Class-D small amplifier
I hope it will be much smaller than ver01.
Schematic
Board Image. Almost half size and soldering than Ver.01.
Ver.03
Previous designs are hanging up to 44.1kHz!
There is 11.2896MHz MCLK to be used for calculation.
( x 256 time width control can reduce drivers)
and CPLD should be changed to FPGA, to contain "delay control register".
It can reduce spacers to adjust focusing point.
Schematic of One Module
- Analog Switch, Emitter-Follower is fast enough to handle 11.2896MHz
- Vref will be (Voltage at Volume) /2, /4, /8, /16, /32, /64, /128 for 7 speakers
- Each Vref should be stabilized by OpAmp.
- PCM value > 0 then Positive side driven. else Negative side driven.
- Positive/Negative Pulse width are controlled by FPGA, 11.2896MHz = 256 x 44.1kHz
- 256 drive power control x 256 drive width control = 65536 = 16bits PCM full range of value
(to be continued)
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