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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:43:41 04/01/2008 
-- Design Name: 
-- Module Name:    FX2_I2S - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FX2_I2S is
    Port ( FX2_CLK  : in  STD_LOGIC;
           FX2_FD   : in  STD_LOGIC_VECTOR (7 downto 0);
           FX2_flags_0 : in  STD_LOGIC;	--FIFO2 flag. when data exist, =1.
           FX2_PA_2 : out  STD_LOGIC;		--OE to FX2. =0 to read.
           FX2_PA_4 : out  STD_LOGIC;	   --FIFO select address. 0.
           FX2_PA_5 : out  STD_LOGIC;	   --FIFO select address. 0.
           FX2_SLRD : out  STD_LOGIC);		--FIFO Read Signal. =0 to read.
end FX2_I2S;

architecture Behavioral of FX2_I2S is

type STATE_FX2 is (S0, S1, S2, S3);
signal FX2State 	: STATE_FX2;

begin
	FX2STATE_UPDATE: process(FX2_CLK, FX2_flags_0)
	begin
		if FX2_CLK' event and FX2_CLK = '1' then
			case FX2State is
				when S0 => 	if (FX2_flags_0 = '1') then
									FX2State <= S1;	-- Start Transfer Cycle
								else
									FX2State <= S0;	-- stay S0.
								end if;
				when S1 =>	FX2State <= S2;
				when S2 =>	FX2State <= S3;		
				when S3 => 	FX2State <= S0;
				when others => FX2State <= S0;
			end case;
		end if;
	end process;
	
	OUTPUT_Control: process(FX2State)
	begin
		--initialize for Output Signal
		FX2_PA_2 <= '1';
		FX2_PA_4 <= '0';
		FX2_PA_5 <= '0';
		FX2_SLRD <= '1';
		-- Decode "Transfer Cycle state" to Output signal
		case FX2State is
			when S0	=> null;
			when S1	=> FX2_PA_2 <= '0'; FX2_SLRD <= '1';
			when S2	=> FX2_PA_2 <= '0'; FX2_SLRD <= '0';
			when S3	=> FX2_PA_2 <= '1'; FX2_SLRD <= '1';
			when others	=> null;
		end case;
	end process;

end Behavioral;