---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:43:41 04/01/2008 -- Design Name: -- Module Name: FX2_I2S - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FX2_I2S is Port ( FX2_CLK : in STD_LOGIC; CLK_11 : in STD_LOGIC; FX2_FD : inout STD_LOGIC_VECTOR (7 downto 0); FX2_flags_0 : in STD_LOGIC; --FIFO2 flag. when data exist, =1. FX2_PA_2 : out STD_LOGIC; --OE to FX2. =0 to read. FX2_PA_4 : out STD_LOGIC; --FIFO select address. 0. FX2_PA_5 : out STD_LOGIC; --FIFO select address. 0. FX2_SLRD : out STD_LOGIC; --FIFO Read Signal. =0 to read. FX2_SLWR : out STD_LOGIC; --FIFO Write Signal. =0 to read. --debug signals Debug_FX2_flags_0 : out STD_LOGIC; Debug_FX2_PA_2 : out STD_LOGIC; Debug_FX2_SLRD : out STD_LOGIC); end FX2_I2S; architecture Behavioral of FX2_I2S is -- Internal Signal type STATE_FX2 is (S0, S1, S2, S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15); type STATE_I2S is (I0, I1, I2, I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15); signal FX2State : STATE_FX2; signal D1 : STD_LOGIC_VECTOR (7 downto 0); signal FPGAOE : STD_LOGIC; -- 1=enable, 0=ZZZZ signal D2 : STD_LOGIC_VECTOR (7 downto 0); signal I2SState : STATE_I2S; signal R : STD_LOGIC; signal S : STD_LOGIC; signal Q : STD_LOGIC; --signal in_Debug_FX2_flags_0 : STD_LOGIC; begin RS_FF: process(R,S) begin if (R = '1' and S = '0') then -- RESET Q <= '0'; elsif (R = '0' and S = '1') then -- SET Q <= '1'; elsif (R = '1' and S = '1') then -- prohibit Q <= '0'; end if; end process; --Common Logic DEBUG_READ: process(FX2_flags_0) begin Debug_FX2_flags_0 <= FX2_flags_0; end process; -- 11.2896MHz side I2SSTATE_UPDATE: process(CLK_11, Q) begin if rising_edge(CLK_11) then case I2SState is when I0 => if (Q = '1') then I2SState <= I1; R <= '1'; else I2SState <= I0; R <= '0'; end if; when I1 => I2SState <= I2; R <= '0'; when I2 => I2SState <= I3; R <= '0'; when I3 => I2SState <= I4; R <= '0'; when I4 => I2SState <= I5; R <= '0'; when I5 => I2SState <= I6; R <= '0'; when I6 => I2SState <= I7; R <= '0'; when I7 => I2SState <= I0; R <= '0'; -- when I8 => I2SState <= I9; R <= '0'; -- when I9 => I2SState <= I10; R <= '0'; -- when I10 => I2SState <= I11; R <= '0'; -- when I11 => I2SState <= I12; R <= '0'; -- when I12 => I2SState <= I13; R <= '0'; -- when I13 => I2SState <= I14; R <= '0'; -- when I14 => I2SState <= I15; R <= '0'; -- when I15 => I2SState <= I0; R <= '0'; when others => I2SState <= I0; R <= '0'; end case; end if; end process; -- FX2 side FX2STATE_UPDATE: process(FX2_CLK, FX2_flags_0, Q) begin if rising_edge(FX2_CLK) then case FX2State is when S0 => if (FX2_flags_0 = '1') then FX2State <= S1; -- Start Transfer Cycle else FX2State <= S0; -- stay S0. end if; when S1 => FX2State <= S2; when S2 => FX2State <= S3; when S3 => if (Q = '0') then FX2State <= S0; else FX2State <= S3; end if; -- when S4 => FX2State <= S5; -- when S5 => FX2State <= S6; -- when S6 => FX2State <= S7; -- when S7 => FX2State <= S0; -- when S8 => FX2State <= S9; -- when S9 => FX2State <= S10; -- when S10 => FX2State <= S11; -- when S11 => FX2State <= S12; -- when S12 => FX2State <= S13; -- when S13 => FX2State <= S14; -- when S14 => FX2State <= S15; -- when S15 => FX2State <= S0; when others => FX2State <= S0; end case; end if; end process; OUTPUT_Control: process(FX2_CLK, FX2State, FX2_FD) begin if falling_edge(FX2_CLK) then --initialize for Output Signal FX2_PA_2 <= '1'; Debug_FX2_PA_2 <= '1'; FX2_PA_4 <= '0'; FX2_PA_5 <= '0'; FX2_SLRD <= '1'; Debug_FX2_SLRD <= '1'; FX2_SLWR <= '1'; FPGAOE <= '0'; -- Decode "Transfer Cycle state" to Output signal case FX2State is when S0 => FX2_PA_2 <= '1'; FX2_SLRD <= '1'; FX2_SLWR <= '1'; Debug_FX2_PA_2 <= '1'; Debug_FX2_SLRD <= '1'; D1 <= "00000000"; D2 <= D2; S <= '0'; FPGAOE <= '0'; FX2_PA_4 <= '0'; FX2_PA_5 <= '0'; when S1 => FX2_PA_2 <= '0'; FX2_SLRD <= '1'; FX2_SLWR <= '1'; Debug_FX2_PA_2 <= '0'; Debug_FX2_SLRD <= '1'; D1 <= "00000000"; D2 <= D2; S <= '0'; FPGAOE <= '0'; FX2_PA_4 <= '0'; FX2_PA_5 <= '0'; when S2 => FX2_PA_2 <= '0'; FX2_SLRD <= '0'; FX2_SLWR <= '1'; Debug_FX2_PA_2 <= '0'; Debug_FX2_SLRD <= '1'; D1 <= FX2_FD; D2 <= D2; S <= '0'; FPGAOE <= '0'; FX2_PA_4 <= '0'; FX2_PA_5 <= '0'; when S3 => FX2_PA_2 <= '1'; FX2_SLRD <= '1'; FX2_SLWR <= '1'; Debug_FX2_PA_2 <= '1'; Debug_FX2_SLRD <= '1'; D1 <= D1; D2 <= D2; S <= '1'; FPGAOE <= '0'; FX2_PA_4 <= '0'; FX2_PA_5 <= '0'; --write cycle -- when S4 => -- FX2_PA_2 <= '1'; -- FX2_SLRD <= '1'; -- FX2_SLWR <= '1'; -- Debug_FX2_PA_2 <= '1'; -- Debug_FX2_SLRD <= '1'; -- D1 <= D1; -- D2 <= D1; -- S <= '0'; -- FPGAOE <= '0'; -- FX2_PA_4 <= '0'; -- FX2_PA_5 <= '1'; -- when S5 => -- FX2_PA_2 <= '1'; -- FX2_SLRD <= '1'; -- FX2_SLWR <= '0'; -- Debug_FX2_PA_2 <= '1'; -- Debug_FX2_SLRD <= '1'; -- D1 <= D1; -- D2 <= D2; -- S <= '0'; -- FPGAOE <= '1'; -- FX2_PA_4 <= '0'; -- FX2_PA_5 <= '1'; -- when S6 => -- FX2_PA_2 <= '1'; -- FX2_SLRD <= '1'; -- FX2_SLWR <= '1'; -- Debug_FX2_PA_2 <= '1'; -- Debug_FX2_SLRD <= '1'; -- D1 <= D1; -- D2 <= D2; -- S <= '0'; -- FPGAOE <= '1'; -- FX2_PA_4 <= '0'; -- FX2_PA_5 <= '1'; -- when S7 => -- FX2_PA_2 <= '1'; -- FX2_SLRD <= '1'; -- FX2_SLWR <= '1'; -- Debug_FX2_PA_2 <= '1'; -- Debug_FX2_SLRD <= '1'; -- D1 <= D1; -- D2 <= D2; -- S <= '0'; -- FPGAOE <= '0'; -- FX2_PA_4 <= '0'; -- FX2_PA_5 <= '1'; when others => null; end case; end if; end process; BiDir_Control: process(FPGAOE,D1) begin if (FPGAOE='0') then FX2_FD <= "ZZZZZZZZ"; else FX2_FD <= D1; end if; end process; end Behavioral;